1. Field of the Invention
This invention relates generally to processor-based systems, and, more particularly, to a pipelined serial ring bus for use in a processor-based system.
2. Description of the Related Art
Conventional processor-based systems typically include one or more processors such as a central processing unit (CPU), a graphical processing unit (GPU), an accelerated processing unit (APU), and the like. The processor(s) are configured to access instructions and/or data that are stored in a main memory and then execute the instructions and/or manipulate the data. The processor(s) include one or more processor cores that are used to execute the instructions and/or manipulate the data. Most (if not all) processor(s) also implement a hierarchical (or multilevel) cache system that is used to speed access to the instructions and/or data by storing selected instructions and/or data in the caches. Conventional processor(s) also typically include numerous other physical and/or logical blocks that are used to implement other functionality used by the processor. Exemplary physical and/or logical blocks include data caches, retirement blocks, dispatch blocks, decoders, flops, tag arrays, translation lookaside buffers, and the like.
The functional blocks in the processor can be configured using registers that are connected to the functional blocks. For example, model specific registers (MSRs) can be used to store bits of information that are used to configure the associated functional block. A typical MSR includes 64 bits that can be used to define or initialize a state of the associated functional block. Microcode implemented in the processor core(s) can access the information in the MSRs and can be used to set the appropriate values of the bits in each MSR, e.g., to configure the functional blocks for particular applications or conditions within the processor. The microcode can access information in the MSRs and convey new information to the MSRs over one or more buses that communicatively couple the processor core(s) to the other functional blocks in the processor. For example, the processor core(s) and the functional blocks can be communicatively coupled by one or more buses. Each element that is coupled to the bus has an address so that instructions and/or data can be placed on the bus and delivered to the MSR indicated by the bus address. One instruction at a time is placed on the bus, which simplifies the microcode that is used to set the values in the MSRs.